You are a dynamic and highly motivated engineer with at least four years of experience in digital IC design * You have experience with front-end ASIC or FPGA design in VHDL and/or Verilog and/or SystemVerilog * Experience with any of the following protocols and techniques is a plus: SPI, I2C, UART, CAN, LIN, SENT, DSP, CRC, FSM design, MCU * Study, specification, design and verification of high-quality digital and mixed-signal ICs * Coach junior engineers in design, verification and testing of integrated circuits and improve their level of technical expertise and knowledge of the total business * You have experience with front-end verification, preferably in SystemVerilog + UVM, to write directed tests, constrained ra
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