We are seeking an experienced Senior Analog Layout Engineer to design and integrate complex analog and GPIO circuits for advanced process technologies (e.g., TSMC 16nm and below) as well as deep sub-micron nodes. This role requires close collaboration with analog design, PDK, and EDA tool teams to deliver robust, high-quality layouts that meet stringent foundry and reliability standards. * Execute end-to-end schematic-to-layout design for analog and GPIO circuits. * 8+ yearsof hands-on experience in analog/mixed-signal IC layout for advanced FinFET and CMOS technologies. * Solid grasp of analog layout fundamentals —including matching, shielding, low-n
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