We are seeking an experienced Senior Analog Layout Engineer to design and integrate complex analog and GPIO circuits for advanced process technologies (e.g., TSMC 16nm and below) as well as deep sub-micron nodes. As part of our innovative research team, you will take full ownership of schematic-to-layout implementation, top-level integration, and layout sign-off-ensuring best-in-class performance, reliability, and manufacturability. * Strong understanding of PCELLS/pycellsPDK Components, floor planning, power grid, IO ring, and ESD integration , .
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