As part of our innovative research team, you will take full ownership of schematic-to-layout implementation, top-level integration, and layout sign-off-ensuring best-in-class performance, reliability, and manufacturability. This role requires close collaboration with analog design, PDK, and EDA tool teams to deliver robust, high-quality layouts that meet stringent foundry and reliability standards. * Optimize layout for matching, symmetry, shielding, and parasitic control to achieve superior performance and yield. * Participate in cross-functional reviews to maintain high-quality standards and continuous improvement. * Strong understanding of PCELLS/pycellsPDK Components, floor planning, power grid, IO ring, and ESD integration , . * In-depth knowledge of Layout-Dependent Effects (LDE) , EM/IR analysis, and reliability considerations.
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