Technical team lead for the digital content of mixed-signal ASICs including interaction with customers, suppliers and the internal ASIC development team * Work together with international customers and communicate efficiently to successfully complete the project * You are a dynamic and highly motivated engineer with at least four years of experience in digital IC design * You have experience with front-end ASIC or FPGA design in VHDL and/or Verilog and/or SystemVerilog * You have experience with front-end verification, preferably in SystemVerilog + UVM, to write directed tests, constrained randomized tests and to gather and interpret metrics such as code/condition/FSM/toggle/functional coverage * You have experience with digital synthesis, logic equivalence checking (LEC) and Static Timing Analysis (STA) * Experience with UPF and/or CPF and DFT and ATPG is a plus
more
